Exemplary embodiments relate to a page buffer circuit and, more particularly, to a page buffer circuit having a reduced area by reducing the number of elements.
Semiconductor memory devices may be configured to store data and allow stored data to be read therefrom. Typical examples of semiconductor memory devices are volatile memory devices configured to have its stored data erased when power is off and nonvolatile memory devices configured to retain its data even when power is off. Flash memory of the nonvolatile memory devices has been widely used for computers, memory cards, etc. because it is capable of batch-erasing data of a cell electrically.
The flash memory devices may be classified into NOR-type flash memory and NAND-type flash memory based on a coupling state between a cell and a bit line. The NOR-type flash memory is configured to have two or more cell transistors coupled in parallel to one bit line, to store data using a channel hot electron method, and to erase data using a Fowler-Nordheim (F-N) tunneling method. The NAND-type flash memory is configured to have two or more cell transistors coupled in series to one bit line and to store or erase data using the F-N tunneling method. In general, the NOR-type flash memory is not as suitable as NAND-type flash memory for high integration due to its high current consumption, but has a benefit in that it is suitable for high speed operations. The NAND-type flash memory is comparatively more suitable for high integration since it uses less current than the NOR-type flash memory.
Conventional nonvolatile memory device may include a memory cell array configured to store data, page buffers coupled to bit lines of the memory cell array, a Y decoder configured to supply the page buffers with a data IO path, an X decoder configured to couple the word lines of the memory cell array with a global word line for supplying a voltage, a voltage supply unit configured to generate voltages and supply them to the global word line, and a control unit configured to control an overall operation.
FIG. 1 is a circuit diagram of a conventional page buffer.
Referring to FIG. 1, the page buffer 100 includes a sensing unit 110, a precharge unit 120, a data transmission unit 130, a data latch unit 140, and a data change unit 150.
The sensing unit 110 is coupled with a bit line and is configured to sense a bit line voltage and change a voltage level of a sense node SO. The precharge unit 120 is configured to precharge the sense node SO.
The data transmission unit 130 is configured to transfer data, stored in the data latch unit 140, to the sense node SO and to provide a data transmission path for transferring data to be latched by latches of the data latch unit 140.
The data latch unit 140 includes first and second latches L1, L2. Each of the latches is configured to latch data for a program or to read data stored in a memory cell and store the read data. The data change unit 150 is configured to input data to the first and second latches L1, L2 in response to a voltage level of the sense node SO.
The sensing unit 110 includes a first NMOS transistor N1. The precharge unit 120 includes a first PMOS transistor P1. The data transmission unit 130 includes second to fifth NMOS transistors N2 to N5. The data latch unit 140 includes first to fourth inverters I1 to I4. The data change unit 150 includes sixth to ninth NMOS transistors N6 to N9.
The second and third NMOS transistors N2 and N3 operate to transmit data of the first latch L1, and the fourth and fifth NMOS transistors N4, N5 operate to transmit data of the second latch L2.
The first and second inverters I1, I2 form the first latch L1, and the third and fourth inverters I3, I4 form the second latch L2. Furthermore, the sixth and seventh NMOS transistors N6, N7 operate to transfer data to or from the first latch L1, and the eighth and ninth NMOS transistors N8, N9 operate to transfer data to or from the second latch L2.
In the page buffer circuit described above, when the number of data bits stored in a memory cell increases, the number of latches is increased. Here, in the data transmission unit 130 and the data change unit 150, with an increase in the number of latches, the number of transistors for transferring data to or from each latch is also increased. Such an increase of the transistors for data transfer corresponding to the increase of the latches causes an increase in the overall size of a page buffer.
In particular, consistent with the recent development of a multi-level cell (MLC) capable of storing a greater amount of bit information, the number of latches in a page buffer and thus the number of accompanying transistors is inevitably increased. Such an increase in the number of elements is a concern in light of efforts to reduce the overall size of a memory device.